`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/12/24 09:51:23
// Design Name: 
// Module Name: Smart_Router_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Smart_Router_tb();

reg  clk, rst_n;
reg  [31:0] i_flit [0:3]; // E-W-N-S-L
wire [31:0] o_flit [0:3]; // E-W-N-S-L

SmartRouter #(
    .DataWidth('d32),
    .FifoDepth('d4),
    .VCNumber('d4),
    .CoreID(6'd1)
) UUT (
    .clk(clk),
    .rst_n(rst_n),
    
    .i_data_e(i_flit[0]), .i_data_w(i_flit[1]), 
    .i_data_n(i_flit[2]), .i_data_s(i_flit[3]), 
    .i_data_l(i_flit[4]),
    .i_credit_e(8'd0), .i_credit_w(8'd0), 
    .i_credit_n(8'd0), .i_credit_s(8'd0), 
    .i_credit_l(8'd0), 

    .o_data_e(o_flit[0]), .o_data_w(o_flit[1]), 
    .o_data_n(o_flit[2]), .o_data_s(o_flit[3]), 
    .o_data_l(o_flit[4]),
    .o_credit_e(), .o_credit_w(), 
    .o_credit_n(), .o_credit_s()
);

initial begin            
    $dumpfile("wave.vcd");
    $dumpvars(0, Smart_Router_tb);
end

initial begin
    clk = 0; rst_n = 1;
    i_flit[0] = 32'b0; i_flit[1] = 32'b0; i_flit[2] = 32'b0;
    i_flit[3] = 32'b0; i_flit[4] = 32'b0; #7
    rst_n = 0; #20 rst_n = 1;
    // 000011 000001 -> [0000][11 00][0001] -> 0C1
    @(posedge clk) #0 i_flit[0] = 32'h40_4_0C1_0_0; #20 // Core 1 -> 3 (head)
    @(posedge clk) #0 i_flit[0] = 32'hAB_C_023_8_1; #20 // Core 1 -> 3 (body) # ABC0238
    @(posedge clk) #0 i_flit[0] = 32'hBC_D_6F1_2_1; #20 // Core 1 -> 3 (body) # BCD6F12
    @(posedge clk) #0 i_flit[0] = 32'hCD_E_6F1_2_F; #20 // Core 1 -> 3 (tail) # CDE6F12
    // 000001 000000 -> 040
    @(posedge clk) #0 i_flit[0] = 32'h40_1_040_0_0; #20 // Core 1 -> 3 (head)
    @(posedge clk) #0 i_flit[0] = 32'hAB_C_233_8_1; #20 // Core 1 -> 3 (body) # ABC2338
    @(posedge clk) #0 i_flit[0] = 32'hBC_D_233_4_1; #20 // Core 1 -> 3 (body) # BCD2334
    @(posedge clk) #0 i_flit[0] = 32'hCD_E_233_2_F; #20 // Core 1 -> 3 (tail) # CDE2332
    @(posedge clk) #0 i_flit[0] = 32'h0; #100
    $finish(0);
end

always #10 clk = ~clk;
 
endmodule
